The 8051 was designed in 1980 for an 8-bit microcontroller world. The 8051E is the 2026 evolution of that ISA — paged calls deprecated, opcode slots freed for atomic bits, authorisation, safe firmware update, and deterministic system-management primitives. This document is structured in the spirit of the ARM Architecture Reference Manual (ARMv6 → ARMv7): a discipline of removed, replaced, added, and behaviourally-changed ops, with a migration guide and a binary-compatibility matrix.
The 8051 was a product of its era — a small 8-bit core with a paged 11-bit subroutine-call mechanism, hardware decimal-adjust for BCD arithmetic, and a code-memory addressing path bound to the program counter. None of these served a deterministic SoC built around three finite verifiable domains. The 8051E reclaims the freed opcode slots for primitives the modern ISA actually needs.
ACALL and AJMP each occupied 8 opcode slots — one per 2KB code page. In a 32-bit deterministic architecture with linear LCALL/LJMP at 16-bit absolute addresses, the paged variants became 16 opcode slots representing zero new behaviour. Reclaiming them freed exactly the budget needed for atomic-bit, authorisation, update, and system- management classes.
A 2026 deterministic SoC needs: atomic test-and-modify on bit-addressable memory (locks, semaphores), access-policy primitives (boot-loader and security hardware hooks), safe firmware-update FSM (enter / write / verify / commit / abort), and system-management primitives (memory barriers, fault clear, wait-for-event, low-power entry). These are first-class instructions, not library calls.
The architecture is bounded by 2⁸ opcodes. Every freed slot is contested. The five new classes are the smallest set that gives the deterministic SoC its operational backbone without breaking the bounded-domain commitment.
Nineteen opcode slots were reclaimed: 8 ACALL, 8 AJMP, 1 DA, and 2 MOVC variants. None of them carry semantics that cannot be expressed by surviving instructions or by software idiom.
| Mnemonic | Opcode | Bytes | Replacement / rationale |
|---|---|---|---|
| ACALL page0 | 0x11 | 2 | LCALL addr16 (already in ISA, no semantic change) |
| ACALL page1 | 0x31 | 2 | LCALL addr16 |
| ACALL page2 | 0x51 | 2 | LCALL addr16 |
| ACALL page3 | 0x71 | 2 | LCALL addr16 |
| ACALL page4 | 0x91 | 2 | LCALL addr16 |
| ACALL page5 | 0xB1 | 2 | LCALL addr16 |
| ACALL page6 | 0xD1 | 2 | LCALL addr16 |
| ACALL page7 | 0xF1 | 2 | LCALL addr16 |
| Mnemonic | Opcode | Bytes | Replacement / rationale |
|---|---|---|---|
| AJMP page0 | 0x01 | 2 | LJMP addr16 |
| AJMP page1 | 0x21 | 2 | LJMP addr16 |
| AJMP page2 | 0x41 | 2 | LJMP addr16 |
| AJMP page3 | 0x61 | 2 | LJMP addr16 |
| AJMP page4 | 0x81 | 2 | LJMP addr16 |
| AJMP page5 | 0xA1 | 2 | LJMP addr16 |
| AJMP page6 | 0xC1 | 2 | LJMP addr16 |
| AJMP page7 | 0xE1 | 2 | LJMP addr16 |
| Mnemonic | Opcode | Bytes | Replacement / rationale |
|---|---|---|---|
| DA A | 0xD4 | 1 | Manual BCD adjust if required (no hardware decimal-adjust path) |
| MOVC A, @A+PC | 0x83 | 1 | DPTR-based constant access — MOVX A, @DPTR after constant-domain load |
| MOVC A, @A+DPTR | 0x93 | 1 | MOV DPTR, A (0x83 reused) + MOVX A, @DPTR |
Seventeen opcodes across five classes. Each class is scoped to a single architectural concern and respects the TDM read-only sideband — ISA does not edit TDM operands.
Direct transfer between IRAM and XDATA through DPTR. TDM is read-only sideband; ISA does not edit TDM.
| Mnemonic | Opcode | Bytes | Flags |
|---|---|---|---|
| MOVX iram_addr, @DPTR | 0x01 | 2 | — |
| MOVX @DPTR, iram_addr | 0x21 | 2 | — |
Atomic test-and-modify over bit-addressable domain. Previous bit value returns in C.
| Mnemonic | Opcode | Bytes | Flags |
|---|---|---|---|
| TSET bit_addr16 | 0x41 | 3 | C |
| TCLR bit_addr16 | 0x61 | 3 | C |
Hooks into SFR/security hardware. No immediate auth fields; no editable TDM operands.
| Mnemonic | Opcode | Bytes | Flags |
|---|---|---|---|
| AUTHCHK A | 0x81 | 1 | C |
| AUTHLD A, @DPTR | 0xA1 | 1 | — |
| AUTHSET A | 0xC1 | 1 | — |
| AUTHCLR | 0xE1 | 1 | — |
Safe update state-machine hooks: enter, write, verify, commit, abort.
| Mnemonic | Opcode | Bytes | Flags |
|---|---|---|---|
| UPDENTER | 0x11 | 1 | — |
| UPDWR @DPTR, A | 0x31 | 1 | — |
| UPDCRC A | 0x51 | 1 | C |
| UPDCOMMIT | 0x71 | 1 | C |
| UPDABORT | 0xD4 | 1 | — |
Bus ordering, fault recovery, wait-for-event and low-power entry hooks.
| Mnemonic | Opcode | Bytes | Flags |
|---|---|---|---|
| MEMBAR | 0x91 | 1 | — |
| FAULTCLR | 0xB1 | 1 | — |
| WFE | 0xD1 | 1 | — |
| SLEEP | 0xF1 | 1 | — |
Opcode 0x83 (formerly MOVC A,@A+PC) is reused for MOV DPTR, A. This is the canonical entry point for the constant-domain
access pattern: load DPTR from A, then MOVX A,@DPTR for the constant fetch.
The 8051E permits a curated set of decode-stage instruction fusions for predictable micro-op sequences. The whitelist is fixed; fusion never derives from cross-field interaction. Internals are out of public scope (see §14 IP fence).
Subroutine return semantics are normalised — the return-address stack discipline is single-shape, with no implicit fix-up paths. Trace decode is computable from the architectural state alone.
The xDATA address space supports two architectural lanes for parallel constant / IRAM-bridged transfers. The dual-lane mechanic is a property of the LSU; ISA exposes it through MOVX_IRAM (§3) without surfacing arbitration internals.
TSET / TCLR perform atomic test-and-modify on a 16-bit bit address. Previous bit value returns in C; no observable intermediate state is exposed at the bus boundary. Memory barrier semantics are explicit (MEMBAR, §3 SYSTEM_MANAGEMENT).
UPDATE class implements a five-state FSM: idle → entered → writing →
verified → committed, with aborted as a parallel exit from any
non-idle state. Each transition is gated by an instruction; no implicit state
progression.
For legacy 8051 code being ported to 8051E:
| Legacy pattern | 8051E equivalent | Effort |
|---|---|---|
| ACALL pagen | LCALL addr16 (already in legacy ISA) | Mechanical assembler-level rewrite. No semantic change. |
| AJMP pagen | LJMP addr16 | Mechanical assembler-level rewrite. No semantic change. |
| DA A (decimal-adjust) | Software BCD adjust path | Manual inline expansion. Affects only BCD-arithmetic call sites. |
| MOVC A, @A+PC | MOV DPTR, A (0x83) + MOVX A, @DPTR | Pattern rewrite. Constant-domain access is now address-independent — porting often simplifies the surrounding code. |
| MOVC A, @A+DPTR | MOVX A, @DPTR after constant-domain load | Pattern rewrite. Same simplification as above. |
Most legacy ALU and transfer ops carry through binary-compatibly. The migration touches flow-control and code-memory access patterns — not arithmetic or data movement — so well-structured legacy firmware ports cleanly with assembler-level changes.
| Category | Status | Notes |
|---|---|---|
| ALU ops (ADD/ADDC/SUBB/INC/DEC/MUL/DIV) | binary-compatible | Edited const16 forms add new addressing modes; legacy 8-bit forms preserved. |
| Logical ops (ANL/ORL/XRL) | binary-compatible | Same — new forms additive, legacy preserved. |
| Bit ops (CLR/SETB/CPL/MOV bit, JBC/JB/JNB) | binary-compatible | Plus new TSET / TCLR (atomic) on freed AJMP slots. |
| Transfer (MOV / MOVX between A, IRAM, DPTR) | binary-compatible | Plus new MOVX iram,@DPTR and MOVX @DPTR,iram via reused AJMP page0/1 slots. |
| Control flow (LCALL / LJMP / RET / RETI / JMP @A+DPTR) | binary-compatible | Paged ACALL / AJMP variants removed (§2); rewrite assembler. |
| BCD adjust (DA A) | re-translation required | Software BCD path replaces hardware DA. Touches call sites only. |
| Code-memory tables (MOVC A,@A+PC / @A+DPTR) | re-translation required | Migrate to DPTR-based constant access; constant domain is address-independent and decoupled from physical code memory layout. |
| NEW: Atomic bit / Auth / Update / System-management | new in 8051E | Seventeen new opcodes. No legacy equivalent — additive functionality. |
The full instruction-set spec — every form, opcode, byte count, flag effect, and the edited const16 / bit addr16 forms — is published as a TOON-format machine-readable document. NDA-gated technical brief covers the encoding tables, fusion whitelist, and the address-space layout.